PlayStation 1 SoC Architecture: CPU, Coprocessors, and Memory Design
This article dissects the architecture of the original PlayStation's System-on-Chip (SoC), focusing on its MIPS R3000A-based CPU, specialized coprocessors (Geometry Transformation Engine, Motion Decoder), and memory subsystem. It highlights the design choices made to balance performance and cost for 3D graphics and multimedia processing in a 90s console.
Read original on Hacker NewsThe original PlayStation's architecture provides a fascinating case study in early SoC design, demonstrating how custom hardware and carefully chosen components were integrated to achieve specific performance goals within strict cost constraints. The core of the system was a MIPS R3000A-based CPU, complemented by several specialized coprocessors that offloaded computationally intensive tasks, particularly for 3D graphics and video decompression.
The MIPS R3000A CPU Core
Sony selected a licensed MIPS R3000A CPU core, manufactured by LSI Logic. This 32-bit RISC processor, running at 33.87 MHz, included a 5-stage pipeline and a 4KB instruction cache. Notably, it lacked a data cache, instead utilizing a 1KB 'Scratchpad' as fast SRAM. This decision reflects a trade-off: simplifying cache coherence for parallel access to specialized hardware, while relying on the programmer to manage critical data in the Scratchpad for performance.
Specialized Coprocessors for Performance
To handle the demanding requirements of 3D graphics and multimedia, Sony integrated three key coprocessors with the CPU:
- System Control Coprocessor (CP0): Standard in MIPS CPUs, it managed cache (instruction and Scratchpad) and handled interrupts/exceptions.
- Geometry Transformation Engine (GTE, CP2): A dedicated math processor for accelerating vector and matrix calculations, 3D projection, lighting, and clipping. This offloaded significant computation from the main CPU, a common pattern in hardware acceleration.
- Motion Decoder (MDEC): Designed to decompress macroblocks (JPEG-like encoded images) at 9,000 macroblocks/second, enabling 320x240 px Full-Motion Video at 30 fps. This was crucial for early game cinematics.
Memory and DMA Architecture
The system featured 2 MB of EDO RAM for general-purpose use. A critical architectural decision was the extensive use of Direct Memory Access (DMA). The CD-ROM controller, MDEC, GPU, SPU, and parallel port could directly access a dedicated DMA controller. This allowed high-throughput data transfers, bypassing the CPU and significantly improving I/O performance. However, a limitation was that the CPU would idle when DMA took control of the main bus, emphasizing the need for efficient data staging in the Scratchpad or careful scheduling.
System Design Lessons
The PlayStation architecture illustrates key system design principles relevant even today: the power of specialized hardware acceleration (GTE, MDEC) to offload main processing units, the importance of efficient I/O via DMA for high-throughput operations, and the trade-offs involved in memory architecture (e.g., Scratchpad over data cache for simplicity and speed in specific scenarios). These decisions were foundational to achieving complex functionalities within the constraints of the era.